In recent years, technology to make a gap between interconnects without filling an insulating film has been developed to suppress the electrical interference between the interconnects as the downscaling of semiconductor devices progresses. However, because there is a tendency for the mechanical strength to decrease for the device structure in which such a gap is formed, there are cases where the occurrence of damage is problematic when planarizing the upper portion of the device structure by CMP (chemical mechanical polishing) technology in the manufacture of the semiconductor device.